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EPVP6300
VFD Controller
Product Specification
VERSION 1.92 ELAN MICROELECTRONICS CORP.
Nov 2004
Trademark Acknowledgments IBM is a registered trademark and PS/2 is a trademark of IBM. Microsoft, MS, MS-DOS, and Windows are registered trademarks of Microsoft Corporation. (c) 2003 ELAN Microelectronics Corporation All Rights Reserved
Printed in Taiwan, ROC, 05/252004 (Version 1.7)
The contents of in this specification are subject to change without notice. ELAN Microelectronics assumes no responsibility for errors that may appear in this specification. ELAN Microelectronics makes no commitment to update, or to keep current, the information contained in this specification. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of the agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics products in such application is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS. Specification Revision History
Version 1.0 1.4 1.5 Initial version 1. 1. 2. 1.6 1.7 1. Revised Display control command Revised error describe Added SPI function timing diagram revise error describe 2004/4/26 2004/06/23 2. Revised external interrupt function (Port9,0 ~ Port9,4) 2004/3/24 Revision Description Date 2003/6/15 2004/1/16
3. Revised display Segment Data Buffers stored registers 2B Add bonding coordinates subsidiary
ADD Relevant Pins assigment ADD Package Information Revices DC Electrical Characteristic Revices cpu Feature Describe additional remark SPI function modify Package Information additional
1.8 1.9 1.91 1.92
2004/8/10 2004/9/16 2004/9/24 2004/11/4
remark Application notes
Revised CONT register describe
Updata Pckage Information
IC name change Revised Operation Voltage VS PLL Operation frequency
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EPVP6300 Specification
Contents
Read Me First! ..............................................................................................................vi 1 2. General Description...............................................................................................1 Feature....................................................................................................................1
2.1 2.2 2.3 2.4 2.5 2.6 2.7 CPU ........................................................................................................................................ 1 SPI.......................................................................................................................................... 1 GPIO....................................................................................................................................... 2 ADC ........................................................................................................................................ 2 VFD ........................................................................................................................................ 2 POR........................................................................................................................................ 2 PACKAGE .............................................................................................................................. 2
3 4 5
Application .............................................................................................................2
VFD controller ..................................................................................................................................... 2
Pin Configuration...................................................................................................3 Functional Block Diagram.....................................................................................4
5.1 Ports Mapping for HV and GPIO ............................................................................................ 5
5.1.1 HV Port Mapping ................................................................................................5 5.1.2 GPIO Port Mapping ............................................................................................5 5.2 6 7 Relevant Pins for programming mode .............................................................5 Pin Descriptions ....................................................................................................6 Function Descriptions ...........................................................................................8
7.1 7.2 Operation Registers Configuration......................................................................................... 8 Operation Registers Description ............................................................................................ 9 7.2.1 R0 (Indirect Address Register) ................................................................................... 9 7.2.2 R1 (TCC) .................................................................................................................... 9 7.2.3 R2 (Program Counter) ................................................................................................ 9 7.2.4 R3 (Status, Page Selection) ..................................................................................... 10 7.2.5 R4 (RAM Selection For Common Registers R20 ~ R3F))........................................ 12 7.2.6 R5 (PORT5 Output Data, Program Page Selection) ................................................ 12 7.2.7 R6 (PORT6 Output Data, SPI Data Buffer) .............................................................. 13 7.2.8 R7 (PORT7 Output Data, ADC , Counter1 Data ...................................................... 14 7.2.9 R8 (PORT8 Output data, Data RAM address) , Counter2_LB data ......................... 16 7.2.10 R9 (PORT9 I/O Data, Data RAM Data Buffer), Counter2_HB Data ................................................................................................... 17
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7.3
7.4 7.5 7.6 7.7
7.2.11 RA (PLL, Main Clock Selection, Watchdog Timer), ADC Output Data Buffer , Counter3 Data................................................................. 18 7.2.12 RB (PORTB I/O Data Buffer, PORT9 Switches)....................................................... 20 7.2.13 RC (PORTC I/O Data , Counter5 Data).................................................................... 21 7.2.14 RD (Interrupt Flag,).................................................................................................. 21 7.2.15 RE (Interrupt Flags, Wake-up)................................................................................. 22 7.2.16 RF (Interrupt Flags) .................................................................................................. 22 7.2.17 R10~R3F (General Purpose Registers) ................................................................... 23 Special Purpose Registers ................................................................................................... 23 7.3.1 A (Accumulator) ........................................................................................................ 23 7.3.2 CONT (Control Register) .......................................................................................... 23 7.3.3 IOC 5 (PORT5 Switches) ......................................................................................... 25 7.3.4 IOC 8 ........................................................................................................................ 25 7.3.5 IOC9 (PORT9 I/O Control) ....................................................................................... 26 7.3.6 IOCA ......................................................................................................................... 27 7.3.7 IOCB (PORTB I/O Control, PORTB Switch) ............................................................ 27 7.3.8 IOCC (PORTC I/O Control) ...................................................................................... 28 7.3.9 IOCD (Interrupt Mask, Prescaler of CN3 ~ CN5) ..................................................... 29 7.3.10 IOCE (Interrupt Mask) .............................................................................................. 29 7.3.11 IOCF (Interrupt Mask ).............................................................................................. 29 Application notes ................................................................................................................... 32 I/O Port ................................................................................................................................. 32 RESET7.4 ..................................................................................................................... 32 Wake Up............................................................................................................................... 33 7.6.1 SLEEP Mode, RA(6 ;7) = 0 + "SLEP" Instruction..................................................... 33 7.6.2 IDLE mode, RA(6 ;7) = 1 + "SLEP" Instruction. ....................................................... 33 7.6.3 Wake-up from SLEEP Mode..................................................................................... 33 7.6.4 Wake-up from IDLE Mode ........................................................................................ 34 Interrupts .............................................................................................................................. 34 Instruction Set ...................................................................................................................... 34 Bonding Coordinates Subsidiary.......................................................................................... 37 7.10.1 Pad Configuration..................................................................................................... 37 7.10.2 Pad Name and Coordinates Table ........................................................................... 38
7.8 7.9 7.10
8
Segment Data Buffers .........................................................................................39
8.1 Commands ........................................................................................................................... 41 8.1.1 Display Mode Setting Command [00]....................................................................... 42 8.1.2 Data Setting Command [01] ..................................................................................... 43 8.1.3 Display Control Command [10] ................................................................................ 44 8.1.4 Address Setting Command [11]................................................................................ 44
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EPVP6300 Specification
9
RC/Crystal OSC....................................................................................................44
9.1 9.2 9.3 9.4 9.5 9.6 General Description.............................................................................................................. 44 Features ............................................................................................................................... 44 Block Diagram ...................................................................................................................... 44 Pin Description ..................................................................................................................... 44 Electrical ............................................................................................................................... 44 Macro Area ........................................................................................................................... 44
10 Absolute Operation Maximum Ratings ..............................................................45 11 DC Electrical Characteristic................................................................................45 12 AC Electrical Characteristic................................................................................46
12.1 12.2 12.3 12.4 CPU Instruction Timing (Ta = -20C ~ 70C, VDD=5V, VSS=0V) ....................................... 46 AC Timing Characteristic (VDD=5V, Ta=+25C) .................................................................. 47 EPVP6300 Operating Voltage (X Axis Min VDD ; Y Axis Main CLK) ......................... 47 AC Timing Diagrams ........................................................................................................... 48
13 Key & Switch Scanning and Display Timing .....................................................49 14 Serial/Parallel Communication Format ..............................................................50
14.1 14.2 Reception (Command/Data Write) ....................................................................................... 50 Transmission (Data Read) ................................................................................................... 50
15 Switching Characteristic Waveform ...................................................................50
15.1 Switching Characteristics (Ta = - 20 to + 70C, VDD = 4.5 to 5.5V, VEE = VDD - 45V) .... 51
16 Serial I/F Sets Display Data Sequence ...............................................................52
16.1 16.2 Updating Display Memory by Incrementing Address ........................................................... 52 Updating Specific Address ................................................................................................... 52
17 Application ...........................................................................................................53
17.1 17.2 17.3 VFD Controller for DVD Player ............................................................................................ 53 VFD Controller for Cascade Applaication............................................................................. 53 APPLICATION CIRCUIT ...................................................................................................... 54
18 Package Information ........................................................................................................ 55
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Read Me First!
Before using the chip, spare a few minutes to take a look at the following important notes. 1. Some bits in the registers are undefined. The values in these bits are unknown and should not be used. These bits are designated with a dash "-" symbol as its bit name in this specification. 2. The following table shows the definitions of the various register designations used to identify bit types, bit name, and bit number. Some definitions will appear quite frequently in the specification.
RA PAGE0
7 RAB7 R/W -0 Bit type Bit name Bit number Register name and its page
6 RAB6 R/W -0
read/write (default value=0)
5 BAB5 R-1
4 RAB4 R/W -1
read/write (default value=1)
3 -
2 RAB2 R
1 RAB1 R-0
0 RAB0 R/W
read/write (w/o default value)
read only (w/o default value)
(undefined) not allowed to use read only (default value=1) read only (default value=0)
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EPVP6300 Specification
EPVP6300
VFD Controller
1
General Description
The EPVP6300 is an 8-bit RISC type vacuum fluorescent display (VFD) controller equipped with low power consumption and high speed CMOS technology. This integrated single chip features on_chip watchdog timer (WDT), one time programming ROM (OTP), data RAM, programmable real time clock/counter, internal interrupt, power down mode, built-in four-wire SPI, 10-bit A/D converter, IR detector, and high voltage output for VFD application.
2. Feature
2.1 CPU
Clock sourceG Crystal Oscillator or RC Oscillator Crystal Oscillator (32.768KHz): with a external crystal RC Oscillator (32.768KHz): with a external 470Kohm resistor 16k x 13 on chip Program ROM. 256 x 8 on chip data RAM 144 x 8 general purpose registers 16 level stack for subroutine nesting 5 channel 8-bit counters: real time clock/counter (TCC) ,COUNTER1, COUNTER3, COUNTER4, COUNTER5 1 channel 16-bit counter: COUNTER2 On-chip watchdog timer (WDT) 99.9H single instruction cycle commands Four operation modes
Mode Sleep mode Idle mode Green mode Normal mode CPU Status Turn off Turn off Turn on Turn on Main Clock Turn off Turn off Turn off Turn on 32.768kHz Clock Status Turn off Turn on Turn on Turn on Description
RA(6) = 0 RA(7) = 0 + "SLEP" instruction RA(6) = 0 RA(7) = 1 +"SLEP" instruction. RA(6) = 0 RA(6) = 1
* Main clock can be programmed from 447.829k to 17.91MH by internal PLL * 8 main clocks: 447.829K, 895.658K, 1.791M , 3.582M , 7.165M , 10.747M , 14.331M and 17.91MHz 13 interrupt source, 5 external (IR , INT1~INT4 ), 8 internal (SPI, ADC, TCC, COUNTER1~5)
2.2 SPI
Serial interface for Clock, Data Input, Data Output, and Strobe pins
This specification is subject to change without further notice.
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2.3 GPIO
GPIO 9 Port(8 bit): general purpose input/output; LED output ;interrupt function GPIO B Port(7 bit): general purpose input/output for power down/MPEG power/Reset control GPIO C Port(8 bit): general purpose input/output for switch and key scanning (12x4 matrix)
2.4 ADC
6 channel 10-bit successive approximation A/D converter Internal (VDD) or external voltage reference
2.5 VFD
Multiple display modes (9-segment & 19-digit to 20-segment & 8-digit) External resistor not necessary for driver outputs.(P-ch open-drain + pull-down resistor output)
2.6 POR
2.0V voltage detector for Power-on reset
2.7 PACKAGE
63-pin die or 64-pin LQFP
3
Application
VFD controller
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VFD Controller
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Pin Configuration
GPIOC6/DOUT
GPIOC5/CLK
GPIOC7/DIN
GPIOC4/STB
GPIO97
GPIO96
GPIOC3
GPIOC2
GPIOC1
GPIOC0
GPIO95
PLLC
OSCI
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 OSCO 1 CRYXRC 2 VSS 3 AVSS 4 GPIOB0 5 GPIOB1 6 GPIOB2 7 GPIOB3 8 GPIOB4 9 GPIOB5 10 GPIOB6 11 AVDD 12 VDD 13 VDD 14 P87(GR1) 15 P86 (GR2 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P85 (GR3) P84 (GR4) P83 (GR5) P82 (GR6) P81 (GR7) P80 (GR8) P77 (GR9/SG20) P76 (GR10/SG190) P75 (GR11/SG18) P74 (GR12/SG17) P73 (GR13/SG16) P72 (GR14/SG15) P71 (GR15/SG14) P67 (GR17/SG12/KS12) P70 (GR16/SG13) P66 (GR18/SG11/KS11) 48 GPIO93 47 GPIO92 46 GPIO91 45 GPIO90 44 /RESET 43 VEE 42 P54 (SG1/KS1)
GPIO94 41 P55 (SG2/KS2) 40 P56 (SG3/KS3) 39 P57 (SG4/KS4) 38 P60 (SG5/KS5) 37 P61 (SG6/KS6) 36 P62 (SG7/KS7) 35 P63 (SG8/KS8) 34 P64 (SG9/KS9) 33 P65 (GR19/SG10/KS10)
NC
NC
EPVP6300 LQFP 64
(62-Pin Die or 64-Pin LQFP-64L)
Fig. 1 Pin Assignment
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Functional Block Diagram
DOUT DIN CLK STB
Serial Data Interface
MCU
8 P87 (GR1) ... P80 (GR8) P77 (GR9/SG20) ... P70 (GR16/SG13) P67 (GR17/SG12/KS12) ... P65 (GR19/SG10/KS10) P64 (SG9/KS9) ... P60 (SG5/KS5) P57 (SG4/KS4) ... P54 (SG1/KS1)
OSCI OSCO
OSC OTP ADC
Segment Driver/ Grid Driver/ High Breakdown Driver
8
3
GPIO9[0:7]
8
Data RAM
5
GPIOB[0:6]
7
Timer GPIO
4
GPIOC[0:7]
8
PLL
IR
Real Time Clock
CRYXRC /RESET
PLLC
VDDx3
VSS
VEE
AVDD
AVSS
Fig. 2a Block Diagram
XIN XOUT PLLC WDT Timer Oscillator Timing Control R1(TCC) Interrupt Control Control Sleep And Wakeup On I/O port General RAM Instruction Decoder Instruction Register ALU R3 R5 ACC ROM Prescaler R2 STACK
Data RAM
R4
Data & Control Bus
IOC5 R5 SPI Port5 (HV)
IOC6 R6 Port6 (HV)
IOC7 R7 Port7 (HV)
IOC8 R8 Port8 (HV)
IOC9 R9 Port9
IOCB RB PortB
IOCC RC PortC
P54~P57
P60~P67
P70~P77
P80~P87
P90~P97
PB0~PB6
PC0~PC3
Fig. 2b Block Diagram 4 of 63
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EPVP6300
VFD Controller
5.1 Ports Mapping for HV and GPIO
5.1.1 HV Port Mapping
Port P54 P55 P56 P57 SG1/KS1 SG2/KS2 SG3/KS3 SG4/KS4 HV Port P60 P61 P62 P63 P64 P65 P66 P67 HV P24/SG5/KS5 P23/SG6/KS6 P22/SG7/KS7 P21/SG8/KS8 P20/SG9/KS9 GR19/P19/SG10/KS10 GR18/P18/SG11/KS11 GR17/P17/SG12/KS12 Port P70 P71 P72 P73 P74 P75 P76 P77 HV GR16/P16/SG13 GR15/P15/SG14 GR14/P14/SG15 GR13/P13/SG16 GR12/P12/SG17 GR11/P11/SG18 GR10/P10/SG19 GR9/P9/SG20 Port P80 P81 P82 P83 P84 P85 P86 P87 HV GR8/P8 GR7/P7 GR6/P6 GR5/P5 GR4/P4 GR3/P3 GR2/P2 GR1/P1
5.1.2 GPIO Port Mapping
Port P90 P91 P92 P93 P94 P95 P96 P97 GPIO GPIO90/LED0/IR Port PB0 GPIO GPIOB0/VREF GPIOB1/AD1 GPIOB2/AD2 GPIOB3/AD3 GPIOB4/AD4 GPIOB5/AD5 GPIOB6/AD6 - Port PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GPIO GPIOC0/Key1 GPIOC1/Key2 GPIOC2/Key3 GPIOC3/Key4 GPIOC4/STB GPIOC5/CLK GPIOC6/DOUT GPIOC7/ DIN Port PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC0 GPIO GPIOC0/Key1 GPIOC1/Key2 GPIOC2/Key3 GPIOC3/Key4 GPIOC4/STB GPIOC5/CLK GPIOC6/DOUT GPIOC0/Key1
GPIO91/LED1/INT1 PB1 GPIO92/LED2/INT2 PB2 GPIO93/LED3/INT3 PB3 GPIO94/LED4/INT4 PB4 GPIO95/LED5 GPIO96/LED6 GPIO97/LED7 PB5 PB6 -
5.2 Relevant Pins for programming mode
OTP PIN NAME VDD VPP DINCK ACLK PGMB OEB DATA GND MASK ROM PIN NAME AVDD /RESTER PC3 PC2 P92 P91 P90 GND
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Pin Descriptions
Pin Name NC VDD I/O # 2 2 Logic power supply 1. Serial Interface Strobe input pin. While the STB goes low, it will cause interrupt event. The data input after the STB has fallen is processed as a command. When this pin is "HIGH," CLK is ignored. 2. Programmable Internal pull high 3. GPIOC4 function 1. Clock input pin. This pin reads serial data at the rising edge and outputs data at the falling edge. 2. Programmable Internal pull high 3. GPIOC5 function 1. Data output pin (N-channel, Open-Drain) 59 DOUT/GPIOC6 I/O 1 2. This pin outputs serial data at the falling edge of the shift clock Schmitt (starting from lower bit). Pull-up 3. Programmable internal pull high 4. GPIOC6 function 1. Data input pin. This pin inputs serial data at the rising edge of the shift clock (starting from lower bit.) Schmitt 2. Programmable Internal pull high Pull-up 3. GPIOC7 function General Purpose I/O pins: 1. Key data input to these pins is latched at the end of display cycle. 2. These pins constitute 4-bit general-purpose input/output port. 3. Programmable Internal Pull-High 4. Wake-up Function Schmitt Pull-up Schmitt Pull-up Description Note
Pin No. 61,62 13,14
57
STB/GPIOC4
I/O
1
Schmitt Pull-up
58
CLK/GPIOC5
I/O
1
60
DIN/GPIOC7
I/O
1
53 - 54
GPIOC0 - GPIOC3
I/O
4
15-22 (B Cell) 23-30 (B Cell)
GR1 - GR8 GR9/P9/SG20
O
8
1. High voltage grid output 2. High breakdown output 1. High voltage grid output 2. High breakdown output 3. High voltage segment output 1. High voltage grid output 2. High breakdown output 3. High voltage segment output 4. Matrix key scan output 1. High breakdown output
-
GR16/ SG13 GR17/SG12/KS12
O
8
31-33 (B Cell)
-
GR19 /SG10/KS10 SG9/KS9 - SG5/KS5
O
3
34-38 (A Cell)
O
5
2. High voltage segment output 3. Matrix key scan output
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VFD Controller
39-42 (C Cell)
1. High voltage segment output SG4/KS4 - SG1/KS1 I/O 4 2. Matrix key scan output 3. General Purpose Input pins: p54~p57 1. General Purpose I/O pins 2. LED output pin (20mA) I/O 8 3. IR Detector 4. Interrupt Function 5. Programmable Internal Pull-High I I I I O 1 1 1 1 1 1 Analog Power Phase Lock Loop Capacitor (connect a Capacitor 0.01 to 0.047u to the Ground). Analog Ground Crystal Oscillator input pin (32, 768KHz) or resister input pin for RC Oscillator Crystal Oscillator output pin (32, 768KHz) Connect this pin to GND of the system General Purpose I/O pins: 1. Power Module CTRL 2. MPEG Power CTRL 3. Reset CTRL 4. ADC/VREF 5. ADC/AD1~AD6 1. Normal (Open)/ 2. Connect to GND / select Crystal Oscillator select RC Oscillator
45 - 52
GPIO90/LED0 - GPIO97/LED7
Schmitt Pull-up
12 63 4 64 1 3
AVDD PLLC AVSS OSCI OSCO VSS
5-11
GPIOB0 - GPIOB6
I/O
7
2 44 43
CRYXRC /RESET VEE
I I -
1 1 1
Pull-up Schmitt
Low active RESET signal input Pull-down level (VDD-(-40V)max)
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Function Descriptions
7.1 Operation Registers Configuration
Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 : 1F 20 : 3F R PAGE Registers R PAGE0 Indirect addressing TCC PC Page, Status RAM bank, RSR Port5 Output data Port6 Output data Port7 Output data Port8 Output data Port9 I/O data PLL, Main clock,WDTE PortB I/O data PortC I/O data Interrupt flag Interrupt flag, Wake-up control Interrupt flag 16 bytes Common registers Bank0 ~ Bank3 Common registers (32x8 for each bank) IOC PAGE Registers IOC PAGE0 IOC PAGE1 R PAGE1 R PAGE2
Program ROM page ADC control Data RAM address Data RAM data buffer ADC output data buffer Port9 pull high PortC pull high SPI data buffer Counter1 data Counter2 LB data Counter2 HB data Counter3 data Counter4 data Counter5 data
Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 8 of 63
Port5 switch
Port9 I/O control
PortB I/O control PortC I/O control Interrupt mask Interrupt mask Interrupt mask
Clock source (CN2,CN1) Prescaler (CN2,CN1) Clock source (CN4,CN3) Prescaler (CN4,CN3) Clock source (CN5) Prescaler (CN5) PortB switch PortC switch
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EPVP6300
VFD Controller
7.2 Operation Registers Description
7.2.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. It is used as indirect address pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). Example: Mov A, @0x20 Mov 0x04, A Mov A, @0xAA Mov 0x00, A ;store an address at R4 for indirect address ;write data 0xAA to R20 at Bank0 through R0
7.2.2 R1 (TCC)
TCC data buffer. Increased by 16.384KHz or by the instruction cycle clock (controlled by CONT register). Written and read by the program as any other register.
7.2.3 R2 (Program Counter)
The structure is depicted in Fig.3 below. Generates 16k x 13 external ROM addresses to the relative programming instruction codes. "JMP" instruction allows the direct loading of the low 10 program counter bits. "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack. "RET'' ("RETL k," "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2, A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0''. "ADD R2, A" allows a relative address to be added to the current PC, and contents of the ninth and tenth bits are cleared to "0''.
R5(PAGE) CALL and INTERRUPT A9 A8 0000 0001 0010 A7~A0 RET RETL RETI STACK1 STACK2 STACK3 STACK4 STACK5 STACK6 STACK7 STACK8 STACK9 STACK10 STACK11 STACK12 STACK13 STACK14 STACK15 STACK16 INTERRUPT ACC,R3,R5(PAGE)
PC
A13 A12 A11 A10
PAGE0 0000~03FF PAGE1 0400~07FF PAGE2 0800~0BFF
restore
store
3 bytes register
1110 1111
PAGE14 3800~3BFF PAGE15 3C00~3FFF
Fig. 3 Program Counter Organization
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"TBL" allows a relative address to be added to the current PC, and the contents of the ninth and tenth bits do not change. The most significant bit (A10~A13) will be loaded with the contents of bit PS0~PS3 in the status register (R5 PAGE 1) upon execution of a "JMP," "CALL," "ADD R2, A." or "MOV R2, A'' instruction. If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at Page0. The CPU will automatically store ACC, R3 status, and R5 PAGE 1, and they will be restored after execution of instruction RETI.
7.2.4 R3 (Status, Page Selection)
(Status Flag, Page Selection Bits)
Bit 7 RPAGE1 R/W-0 Bit 6 R/W-0 Bit 5 R/W-0 Bit 4 T R Bit 3 P R Bit 2 Z R/W Bit 1 DC R/W Bit 0 C R/W RPAGE0 IOCPAGE
Bit 0 (C) : Carry flag
The carry flag is affected by following operation : a. Addition : CF as a carry out indicator, when the addition operation has a carry-out, CF will be "1", in another word, if the operation has no carry-out, CF will be "0". b. Subtraction : CF as a borrow-in indicator, when the subtraction operation must has a borrow-in, the CF will be "0", in another word, if no borrow-in, CF will be "1". c. Comparision : CF is as a borrow-in indicator for Comparision operation as the same as subtraction operation. d. Rotation : CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after rotation.
Bit 1 (DC) : Auxiliary carry flag Bit 2 (Z) : Zero flag
ZF is affected by the result of ALU, if the ALU operation generate a "0" result, the ZF will be "1", otherwise, the ZF will be "0".
Bit 3 (P) : Power down bit Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Time-out bit Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.
Bit 4 (T) :
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VFD Controller
Event WDT wake up from sleep mode WDT time out (not sleep mode) /RESET wake up from sleep Power up Low pulse on /RESET
T 0 0 1 1 x
P 0 1 0 1 X
Remarks
x : don't care
Bit 5 (IOCPAGE) : Change IOC5 ~ IOCE to another page 0/1 IOC page0 / IOC page1 Bit 6 (RPAGE0 ~ RPAGE1) : Change R5 ~ RC to another page (see Section 7.1 Operation Registers Configuration for details.)
(RPAGE1, RPAGE0) (0,0) (0,1) (1,x) R page # selected R page 0 R page 1 R page 2
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7.2.5 R4 (RAM Selection For Common Registers R20 ~ R3F))
(RAM Selection Register)
Bit 7 RB1 R/W-0 Bit 6 RB0 R/W-0 Bit 5 RSR5 R/W Bit 4 RSR4 R/W Bit 3 RSR3 R/W Bit 2 RSR2 R/W Bit 1 RSR1 R/W Bit 0 RSR0 R/W
Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect address for common Registers R20 ~ R3F. RSR bits are used to select up to 32 registers (R20 to R3F) in the indirect address mode. Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common Registers R20 ~ R3F. These selection bits are used to determine which bank is activated among the 4 banks for 32 register (R20 to R3F). Refer to Section 7.1 Operation Registers Configuration for details.
7.2.6 R5 (PORT5 Output Data, Program Page Selection)
a) PAGE 0 (PORT5 Output Data Register for HV or General Purpose Input pins: p54~p57)
Bit 7 P57 W-0 Bit 6 P56 W-0 Bit 5 P55 W-0 Bit 4 P54 W-0 Bit 3 Bit 2 Bit 1 Bit 0 -
b) PAGE 1 (Program ROM Page Register)
Bit 7 AD9 R Bit 6 AD8 R Bit 5 Bit 4 Bit 3 PS3 R/W-0 Bit 2 PS2 R/W-0 Bit 1 PS1 R/W-0 Bit 0 PS0 R/W-0
Bit 0 ~ Bit 3 (PS0 ~ PS3) : Program page selection bits
PS3 PS2 PS1 PS0 0 0 0 0 : : 1 1 0 0 0 0 : : 1 1 0 0 1 1 : : 1 1 0 1 0 1 : : 0 1 Program Memory Page (Address) Page 0 Page 1 Page 2 Page 3 : : Page 14 Page 15
PAGE instruction is used to select the program page to be accessed. The selected program page is maintained by Elan compiler. PAGE instruction will change your program by inserting the instruction within program.
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VFD Controller
7.2.7 R6 (PORT6 Output Data, SPI Data Buffer)
a) PAGE 0 (PORT6 Output Data Register for HV)
Bit 7 P67 W-0 Bit 6 P66 W-0 Bit 5 P65 W-0 Bit 4 P64 W-0 Bit 3 P63 W-0 Bit 2 P62 W-0 Bit 1 P61 W-0 Bit 0 P60 W-0
b) PAGE 2 (SPI Data Buffer)
Bit 7 SPIB7 R/W Bit 6 SPIB6 R/W Bit 5 SPIB5 R/W Bit 4 SPIB4 R/W Bit 3 SPIB3 R/W Bit 2 SPIB2 R/W Bit 1 SPIB1 R/W Bit 0 SPIB0 R/W
Bit 0 ~ Bit 7 (SPIB0 ~ SPIB7) : SPI data buffer If you write data to this register, the data will write to SPIW register. If you read this data, it will read the data from SPIR register. Please refer to the following figure. If you read this data, it will read the data from SPIR register. Please refer to the following figure.
RBF_INT
Read/Write
STB CLK DIN DOUT
Shift Register
STB_INT
Fig. 4a SPI Block Diagram
When Write the data to SPI buffer, the The first byte data by R/W buffer hardware knows for serial output mode sends to the shift register The first byte data by shift register transmission finish & Second byte data by R/W buffer sends to the shift register
STB
DIN
DOUT SCK
STB-INT
RBF-INT
SOUT
SPI function start
The first byte data writer to the SPI buffe SPI data transmission application note:: The following conditions have to conform RBF interrupt flag must =1 RBF interrupt mask must =1 STB must = low CLK must = Hi
The second byte data writer to the SPI buffer The third byte data writer to the SPI buffer
Fig. 4b SPI Timing Diagram
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VFD Controller
7.2.8 R7 (PORT7 Output Data, ADC , Counter1 Data
a) PAGE 0 (PORT7 Output Data Register for HV)
Bit 7 P77 W-0 Bit 6 P76 W-0 Bit 5 P75 W-0 Bit 4 P74 W-0 Bit 3 P73 W-0 Bit 2 P72 W-0 Bit 1 P71 W-0 Bit 0 P70 W-0
b) PAGE 1 (ADC Control Bit)
Bit 7 IN2 R/W-0 Bit 6 IN1 R/W-0 Bit 5 IN0 R/W-0 Bit 4 ADCLK1 R/W-0 Bit 3 ADCLK0 R/W-0 Bit 2 ADPWR R/W-0 Bit 1 ADRES R/W-0 Bit 0 ADST R/W-0
Bit 0(ADST) : AD converter start to sample By setting to "1," the AD will start to sample the data. This bit is automatically cleared by hardware after a sampling. Bit 1(ADRES) : Resolution selection for ADC 0 ADC is an 8-bit resolution When 8-bit resolution is selected, the most significant (MSB) 8-bit data output of the internal 10-bit ADC will be mapped to RA PAGE1. Therefore, R5 PAGE1 Bit 6 ~ 7 will be of no use. 1 ADC is 10-bit resolution When 10-bit resolution is selected, 10-bit data output of the internal 10-bit ADC will be exactly mapped to RA PAGE1 and R5 PAGE1 Bit 6 ~7. Bit 2(ADPWR) : AD converter power control, 1/0 enable/disable
Bit 3 ~ Bit 4 (ADCLK0 ~ ADCLK1) : AD circuit `s sampling clock source. For PLL Clock = 895.658kHz ~ 17.9MHz (CLK2~CLK0 = 001 ~ 110)
ADCLK1 0 0 1 1 ADCLK0 0 1 0 1 Sampling Rate 74.6K 37.4K 18.7K 9.3K Operation Voltage >=3.5V >=3.0V >=2.5V >=2.5V
For PLL Clock = 447.829kHz (CLK2~CLK0 = 000)
ADCLK1 0 0 1 1 ADCLK0 0 1 0 1 Sampling rate 37.4K 18.7K 9.3K 4.7K Operation voltage >=3.0V >=3.0V >=2.5V >=2.5V
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VFD Controller
This is a CMOS multi-channel 10-bit successive approximation A/D converter. Features: 74.6kHz maximum conversion speed at 5V Adjusted full scale input External reference voltage input or internal (VDD) reference voltage 6 analog inputs multiplexed into one A/D converter Power down mode for power saving A/D conversion complete interrupt Interrupt register, A/D control and status register, and A/D data register
Programmable divider 1/Mx fad c
PLL
fpll
fs
Divider Nx
10-bit ADC
ADC output
ADCLK1~ADCLK0
ENPLL
CLK2 ~ CLK0
Fig. 5 ADC Voltage Control Logic
fpll
Mx
fs Nx = 1
fadcon = fadc / 12 Nx = 2 Nx = 4 Nx = 8
14.331MHz 10.747MHz 7.165MHz 3.582MHz 1.791MHz 895.658kHz 447.829kHz
16 12 8 4 2 1 1
895.658kHz 895.658kHz 895.658kHz 895.658kHz 895.658kHz 895.658kHz 447.829kHz
74.638kHz 74.638kHz 74.638kHz 74.638kHz 74.638kHz 74.638kHz 37.391kHz
37.391kHz 37.391kHz 37.391kHz 37.391kHz 37.391kHz 37.391kHz 18.659khz
18.659khz 18.659khz 18.659khz 18.659khz 18.659khz 18.659khz 9.329kHz
9.329kHz 9.329kHz 9.329kHz 9.329kHz 9.329kHz 9.329kHz 4.665kHz
Bit 5 ~ Bit 7 (IN0 ~ IN2) : Input channel selection of AD converter These two bits can choose one of the three AD inputs.
IN2 0 0 0 0 1 1 IN1 0 0 1 1 0 0 IN0 0 1 0 1 0 1 Input AD1 AD2 AD3 AD4 AD5 AD6
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c) PAGE 2 (Counter 1 Data Register)
Bit 7 CN17 R/W-0 Bit 6 CN16 R/W-0 Bit 5 CN15 R/W-0 Bit 4 CN14 R/W-0 Bit 3 CN13 R/W-0 Bit 2 CN12 R/W-0 Bit 1 CN11 R/W-0 Bit 0 CN10 R/W-0
Bit 0 ~ Bit 7 (CN10 ~ CN17) : Counter1 buffer that you can read and write. Counter1 is an 8-bit up-counter with 8-bit prescaler that allows you to use R7 PAGE2 to preset and read the counter (write preset). After an interruption, it will reload the preset value.
7.2.9 R8 (PORT8 Output data, Data RAM address) , Counter2_LB data
a) PAGE 0 (PORT8 Output Data Register for HV)
Bit 7 P87 W-0 Bit 6 P86 W-0 Bit 5 P85 W-0 Bit 4 P84 W-0 Bit 3 P83 W-0 Bit 2 P82 W-0 Bit 1 P81 W-0 Bit 0 P80 W-0
b) PAGE 1 (Data RAM Address Register)
Bit 7 RAM_A7 R/W-0 Bit 6 RAM_A6 R/W-0 Bit 5 RAM_A5 R/W-0 Bit 4 RAM_A4 R/W-0 Bit 3 RAM_A3 R/W-0 Bit 2 RAM_A2 R/W-0 Bit 1 RAM_A1 R/W-0 Bit 0 RAM_A0 R/W-0
Bit 0 ~ Bit 7 (RAM_A0 ~ RAM_A7) : data RAM address
c) PAGE 2 (Counter2 Low Byte Data Register)
Bit 7 CN27 R/W Bit 6 CN26 R/W Bit 5 CN25 R/W Bit 4 CN24 R/W Bit 3 CN23 R/W Bit 2 CN22 R/W Bit 1 CN21 R/W Bit 0 CN20 R/W
Bit 0 ~ Bit 7 (CN20 ~ CN27) : Counter2_LB's buffer that you can read and write. Counter2 is a 16-bit up-counter with 8-bit prescaler that allows you to use R8 PAGE2 to preset and read the counter.(write preset). After an interruption, it will reload the preset value.
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VFD Controller
7.2.10 R9 (PORT9 I/O Data, Data RAM Data Buffer) ,Counter2_HB Data
a) PAGE 0 (PORT9 I/O Data Register)
Bit 7 P97 R/W Bit 6 P96 R/W Bit 5 P95 R/W Bit 4 P94 R/W Bit 3 P93 R/W Bit 2 P92 R/W Bit 1 P91 R/W Bit 0 P90 R/W
Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9(0~7) I/O data register You can use IOC register to define input or output each bit, and to define the pull high condition. Bit 0: 1. P90 2. LED0 3. IR Input : can be defined as Input/Output : can be defined as Output : can be defined as Input and IR is enabled (when IOCF Bit7 is set to 1) Bit 1 ~ Bit4: 1. P91~P94 3. INT1~INT4 Bit 5 ~ Bit7: 1. P95~P97 : can be defined as Input/Output 2. LED5~LED7 : can be defined as Output : can be defined as Input/Output : can be defined as Input 2. LED1~LED4 : can be defined as Output
b) PAGE 1 (Data RAM Data Register)
Bit 7 RAM_D7 R/W Bit 6 RAM_D6 R/W Bit 5 RAM_D5 R/W Bit 4 RAM_D4 R/W Bit 3 RAM_D3 R/W Bit 2 RAM_D2 R/W Bit 1 RAM_D1 R/W Bit 0 RAM_D0 R/W
Bit 0 ~ Bit 7 (RAM_D0 ~ RAM_D7) : Data RAM's data
c) PAGE 2 (Counter2 High Byte Data Register)
Bit 7 CN215 R/W Bit 6 CN214 R/W Bit 5 CN213 R/W Bit 4 CN212 R/W Bit 3 CN211 R/W Bit 2 CN210 R/W Bit 1 CN29 R/W Bit 0 CN28 R/W
Bit 0 ~ Bit 7 (CN28 ~ CN215) : Counter2_HB's buffer that you can read and write. Counter2 is a 16-bit up-counter with 8-bit prescaler that allows you to use R9 PAGE2 to preset and read the counter (write preset). After an interruption, it will reload the preset value.
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7.2.11 RA (PLL, Main Clock Selection, Watchdog Timer), ADC Output Data Buffer , Counter3 Data
a) PAGE 0 (PLL Enable Bit, Main Clock Selection Bits, Watchdog Timer Enable Bit)
Bit 7 IDLE R/W-0 Bit 6 PLLEN R/W-0 Bit 5 CLK2 R/W-0 Bit 4 CLK1 R/W-1 Bit 3 CLK0 R/W-1 Bit 2 Bit 1 Bit 0 WDTEN R/W-0
Bit 0 (WDTEN) : Watch dog control bit You can use WDTC instruction to clear watch dog counter. The counter clock source is 32768/2 Hz. If the prescaler is assigned to TCC, Watch dog will time out by (1/32768 )*2 * 256 = 15.616mS. If the prescaler is assigned to WDT, the time out interval will be longer depending on the prescaler. Ratio. 0/1 Bit 1~Bit 2 : Unused Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits You can select different frequencies for the main clock with CLK1 and CLK2. All the available clock selections are listed below.
PLLEN 1 1 1 1 1 1 1 1 0 CLK2 0 0 0 0 1 1 1 1 CLK1 0 0 1 1 0 0 1 1 CLK0 0 1 0 1 0 1 0 1 Sub clock 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz MAIN clock 447.829kHz 895.658kHz 1.791MHz 3.582MHz 7.165MHz 10.747MHz 14.331MHz 17.91MHz Don't care CPU clock 447.829kHz (Normal mode) 895.658kHz (Normal mode) 1.791MHz (Normal mode) 3.582MHz (Normal mode) 7.165MHz (Normal mode) 10.747MHz (Normal mode) 14.331MHz (Normal mode) 17.91MHz (Normal mode) 32.768kHz (Green mode)
disable/enable
Don't care Don't care Don't care
Bit 6 (PLLEN) :
PLL's power control bit which is CPU mode control register 0/1 disable PLL/enable PLL If PLL is enabled, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode (low frequency, 32768 Hz).
447.8293kHz ~17.9132M Hz
CLK2 ~ CLK0
PLL circuit
ENPLL
1 switch 0 System clock
Sub-clock 32.768kHz
Fig. 6 The Relation Between 32.768kHz and PLL 18 of 63
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VFD Controller
Bit 7 (IDLE) : SLEEP or IDLE mode control as set by SLEP instruction. 0/1 SLEEP mode/IDLE mode. This bit allows SLEP instruction to decide which power saving mode to execute. The status after wake-up and the wake-up source list is as the shown below.
Wakeup Signal SLEEP Mode RA(7,6)=(0,0) + SLEP TCC time out IOCF Bit0=1 COUNTER1 time out IOCF Bit1=1 COUNTER2 time out IOCF Bit2=1 COUNTER3 time out IOCD Bit0=1 COUNTER4 time out IOCD Bit1=1 COUNTER5 time out IOCD Bit2=1 PORT90(IR function) IOCF Bit3=1 WDT time out No function No function No function No function No function No function RA(7,6)=(1,0) + SLEP 1) Wake-up 2) Jump to next instruction after SLEP 1) Wake-up 2) Jump to next instruction after SLEP 1) Wake-up 2) Jump to next instruction after SLEP 1) Wake-up 2) Jump to next instruction after SLEP 1) Wake-up 2) Jump to next instruction after SLEP 1) Wake-up 2) Jump to next instruction after SLEP IDLE Mode
Reset and jump 1) Wake-up to Address 0 2) Jump to next instruction after SLEP Reset and jump 1) Wake-up to Address 0 2) Next instruction
PORTC(0~3)(Key1~Key4) Reset and Jump 1) Wake-up 2) Jump to next instruction after SLEP RE PAGE0 Bit3 or Bit4 or Bit5 or Bit6 = 1 to Address 0 PORT9(1~4) IOCF Bit4 or Bit5 or Bit6 =1 or Bit7=1 Reset and Jump 1) Wake-up to Address 0 2) Jump to next instruction after SLEP
NOTES: 1 PORT90 wakeup function is controlled by IOCF Bit 3. It is a falling edge or rising edge trigger (controlled by CONT register Bit7). 2. PORT91 wakeup function is controlled by IOCF Bit 4. It is a falling edge trigger. 3. PORT92 ~ PORT94 wakeup functions are controlled by IOCF. They are falling edge triggers. 4. PORTC0 ~ PORTC3 wakeup functions are controlled by RE PAGE0 Bit 0 ~ Bit 3. They are falling edge triggers.
b) PAGE 1 (ADC Output Data Register)
Bit 7 AD7 R Bit 6 AD6 R Bit 5 AD5 R Bit 4 AD4 R Bit 3 AD3 R Bit 2 AD2 R Bit 1 AD1 R Bit 0 AD0 R
Bit 0 ~ Bit 7 (AD01~ AD7) : These 8 bits are full ADC data buffer
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c) PAGE 2 (Counter3 Data Register)
Bit 7 CN37 R/W-0 Bit 6 CN36 R/W-0 Bit 5 CN35 R/W-0 Bit 4 CN34 R/W-0 Bit 3 CN33 R/W-0 Bit 2 CN32 R/W-0 Bit 1 CN31 R/W-0 Bit 0 CN30 R/W-0
Bit 0 ~ Bit 7 (CN30 ~ CN37) : Counter3's buffer that you can read and write. Counter3 is an 8-bit up-counter with 8-bit prescaler that allows you to use RA PAGE2 to preset and read the counter (write preset). After an interruption, it will reload the preset value.
7.2.12 RB (PORTB I/O Data Buffer, PORT9 Switches)
a) PAGE 0 (PORTB I/O Data Register)
Bit 7 R-0 Bit 6 PB6 R/W Bit 5 PB5 R/W Bit 4 PB4 R/W Bit 3 PB3 R/W Bit 2 PB2 R/W Bit 1 PB1 R/W Bit 0 PB0 R/W
Bit 0 ~ Bit 6 (PB0 ~ PB6) :
7-bit PORTB (0~6) I/O data register You can use IOC register to define each bit as input or output. When the PORTB is switched to ADC- Bit 0: is defined as VREF Bit 1 ~ Bit 6: is defined as AD1~AD6
b) PAGE 1 (PORT9, Pull High)
Bit 7 PH97 R/W-0 Bit 6 PH96 R/W-0 Bit 5 PH95 R/W-0 Bit 4 PH94 R/W-0 Bit 3 PH93 R/W-0 Bit 2 PH92 R/W-0 Bit 1 PH91 R/W-0 Bit 0 PH90 R/W-0
Bit 0 ~ Bit 7 (PH90 ~ PH97) : PORT9 Bit0 ~ Bit7 pull high control register 0 1 disable pull high function. enable pull high function
c) PAGE 2 (Counter4 Data Register)
Bit 7 CN47 R/W-0 Bit 6 CN46 R/W-0 Bit 5 CN45 R/W-0 Bit 4 CN44 R/W-0 Bit 3 CN43 R/W-0 Bit 2 CN42 R/W-0 Bit 1 CN41 R/W-0 Bit 0 CN40 R/W-0
Bit 0 ~ Bit 7 (CN40 ~ CN47) : Counter4 buffer that you can read and write. Counter 4 is an 8-bit up-counter with 8-bit prescaler that allows you to use RB PAGE2 to preset and read the counter.(write preset). After an interruption, it will reload the preset value.
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VFD Controller
7.2.13 RC (PORTC I/O Data , Counter5 Data)
a) PAGE 0 I/O Data Buffer/Serial Signal
Bit 7 PC7 R/W Bit 6 PC6 R/W Bit 5 PC5 R/W Bit 4 PC4 R/W Bit 3 PC3 R/W Bit 2 PC2 R/W Bit 1 PC1 R/W Bit 0 PC0 R/W
Bit 0 ~ Bit 3 :1. PC0 ~ PC3 are defined as Input/Output 2. KEY1 ~ KEY4 are defined as Keyscan Input Bit 4 Bit 5 Bit 6 Bit 7 :1. PC4 is defined as Input/Output 2. STB = Serial strobe signal :1. PC5 is defined as Input/Output 2. CLK = Serial clock signal :1. PC6 is defined as Input/Output 2. SDO = Serial data out :1. PC7 is defined as Input/Output 2. SDI = Serial data in
b) PAGE 1 (PORTC, Pull High)
Bit 7 PHC7 R/W-0 Bit 6 PHC6 R/W-0 Bit 5 PHC5 R/W-0 Bit 4 PHC4 R/W-0 Bit 3 PHC3 R/W-0 Bit 2 PHC2 R/W-0 Bit 1 PHC1 R/W-0 Bit 0 PHC0 R/W-0
Bit 0 ~ Bit 7 (PHC0 ~ PHC7) : PORTC Bit0 ~ Bit7 pull high control register 0 disable pull high function. 1 enable pull high function
d) PAGE 2 (Counter5 Data Register)
Bit 7 CN57 R/W-0 Bit 6 CN56 R/W-0 Bit 5 CN55 R/W-0 Bit 4 CN54 R/W-0 Bit 3 CN53 R/W-0 Bit 2 CN52 R/W-0 Bit 1 CN51 R/W-0 Bit 0 CN50 R/W-0
Bit 0 ~ Bit 7 (CN50 ~ CN57) : Counter5 buffer that you can read and write. Counter5 is an 8-bit up-counter with 8-bit prescaler that allows you to use RC PAGE2 to preset and read the counter (write preset). After an interruption, it will reload the preset value.
7.2.14 RD (Interrupt Flag,)
a) PAGE 0 (Interrupt Flags Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CNT5 R/W-0 Bit 1 CNT4 R/W-0 Bit 0 CNT3 R/W-0
NOTE: "1" means interrupt request, "0" means non-interrupt
Bit 0 (CNT3) : Counter3 timer overflow interrupt flag. Set when counter3 timer overflows. Bit 1 (CNT4) : Counter4 timer overflow interrupt flag. Set when counter4 timer overflows. Bit 2 (CNT5) : Counter5 timer overflow interrupt flag. Set when counter5 timer overflows.
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7.2.15 RE (Interrupt Flags, Wake-up)
a) PAGE 0 (Interrupt Flags, Wake-up Control Bits)
Bit 7 Bit 6 RBF R/W-0 Bit 5 ADI R/W-0 Bit 4 STB R/W-0 Bit 3 /WUPC3 R/W-0 Bit 2 /WUPC2 R/W-0 Bit 1 /WUPC1 R/W-0 Bit 0 /WUPC0 R/W-0
Bit 0 (/WUPC0) : PORTC0 wake-up control, 0/1 disable/enable PC0 pin wake-up function Bit 1 (/WUPC1) : PORTC1 wake-up control, 0/1 disable/enable PC1 pin wake-up function Bit 2 (/WUPC2) : PORTC2 wake-up control, 0/1 disable/enable PC2 pin wake-up function Bit 3 (/WUPC3) : PORTC3 wake-up control, 0/1 disable/enable PC3 pin wake-up function Bit 4(STB) Bit 5 (ADI) Bit 6 (RBF) : SPI data transfer start interrupt. While the STB signal goes low, it will issue this interrupt. : ADC interrupt flag after sampling : SPI data transfer complete interrupt If the SPI RBF signal contains a rising edge signal, CPU will set this bit (RBF set to "1" after data are completely transferred). : Not used
Bit 7(-)
7.2.16 RF (Interrupt Flags)
a) PAGE 0 (Interrupt Status Register)
Bit 7 INT4 R/W-0 Bit 6 INT3 R/W-0 Bit 5 INT2 R/W-0 Bit 4 INT1 R/W-0 Bit 3 IR R/W-0 Bit 2 CNT2 R/W-0 Bit 1 CNT1 R/W-0 Bit 0 TCIF R/W-0
NOTE: "1" means interrupt request, "0" means non-interrupt
Bit 0 (TCIF) Bit 1 (CNT1) Bit 2 (CNT2) Bit 3 (IR) Bit 4 (INT1) Bit 5(INT2) Bit 6 : (INT3) Bit 7(INT4)
: TCC timer overflow interrupt flag, Set when TCC timer overflows. : Counter1 timer overflow interrupt flag. Set when Counter1 timer overflows. : Counter2 timer overflow interrupt flag. Set when Counter2 timer overflows. : External INT pin interrupt flag. If PORT90 contains a falling /rising edge (controlled by CONT register) trigger signal, CPU will set this bit. : External INT1 pin interrupt flag, If PORT91 contains a falling edge trigger signal, CPU will set this bit. : External INT2 pin interrupt flag. If PORT92 has a falling edge trigger signal, CPU will set this bit. : External INT3 pin interrupt flag. If PORT93 has a falling edge trigger signal, CPU will set this bit. : External IR interrupt flag. If PORT94 has a falling edge trigger signal, CPU will set this bit.
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VFD Controller
Trigger edge is as shown below:
Signal TCC COUNTER1 COUNTER2 COUNTER3 COUNTER4 COUNTER5 IR INT1 INT2 INT3 INT4 Trigger Time out Time out Time out Time out Time out Time out Falling Rising edge Falling edge Falling edge Falling edge Falling edge
7.2.17 R10~R3F (General Purpose Registers)
R10 ~ R1F, R20 ~ R3F (Banks 0 ~ 3) : all are general purpose registers.
7.3 Special Purpose Registers
7.3.1 A (Accumulator)
Internal data transfer, or instruction operand holding. It is not an addressable register.
7.3.2 CONT (Control Register)
CONT register is readable (CONTR) and writable (CONTW).
Bit 7 P90EG Bit 6 INT Bit 5 TS Bit 4 RETBK Bit 3 PAB Bit 2 PSR2 Bit 1 PSR1 Bit 0 PSR0
Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits
PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
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Bit 3 (PAB)
: Prescaler assignment bit 0/1 TCC/WDT When in WDT mode (Bit 3 = 1), the prescaler is cleared by the WDTC and SLEP instructions. Likewise, when in TCC mode (Bit 3 = 0), the prescaler will can NOT be cleared by SLEP instructions. An 8-bit counter is provided as prescaler for the TCC or WDT. The prescaler is available for the TCC only or for the WDT only at a given time. An 8 bit counter is made available for TCC or WDT as determined by the status of Bit 3 (PAB) of the CONT register. Both TCC and prescaler are cleared each time a write to TCC instruction is executed. (See the table above for the prescaler ratio under CONT register and Fig.7 below for the TCC/WDT block diagram.)
Bit 4 (RETBK)
: Return value backup control for interrupt routine 0/1 disable/enable When this bit is set to 1, the CPU will store ACC, R3 status, and R5 PAGE 1 automatically after an interrupt is triggered. It will be restored after instruction RETI. When this bit is set to 0, you need to store ACC, R3, and R5 PAGE 1 in you program.
Bit 5 (TS)
: TCC signal source 0 internal instruction cycle clock timing = ( 2 / system clock) * prescaler* (256 - count vaule) 1 16.384kHz
timing = ( 1 /16.384k) * prescaler * (256 - count vaule)
Bit 6 (INT) : INT enable flag 0 1 Bit 7 (P90EG) 0 1 interrupt masked by DISI or hardware interrupt interrupt enabled by ENI/RETI instructions P90 interruption source is a rising edge signal. P90 interruption source is a falling edge signal.
: Interrupt edge type of P90
16.38KHz
Fig. 7 TCC & WDT Block Diagram 24 of 63
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VFD Controller
7.3.3 IOC 5 (PORT5 Switches)
a) Page 1
Bit 7 P57S R/W-0 Bit 6 P56S R/W-0 Bit 5 P55S R/W-0 Bit 4 P54S R/W-0 Bit 3 Bit 2 Bit 1 Bit 0
Bit 4 ~ Bit 7 (P54S~P57S) : Port5 I/O direction control register 0 set the relative I/O pin as output HV 1 set the relative I/O pin into high impedance
7.3.4 IOC 8
a) PAGE 1 (Clock Source and Prescaler for COUNTER1 and COUNTER2)
Bit 7 CNT2S R/W-0 Bit 6 R/W-0 Bit 5 R/W-0 Bit 4 R/W-0 Bit 3 CNT1S R/W-0 Bit 2 R/W-0 Bit 1 R/W-0 Bit 0 R/W-0 C2_PSC2 C2_PSC1 C2_PSC0 C1_PSC2 C1_PSC1 C1_PSC0
Bit 0 ~ Bit 2 (C1_PSC0 ~ C1_PSC2) : COUNTER1 prescaler ratio Bit 3 (CNT1S) : COUNTER1 clock source 0 16.384kHz
timing = ( 1 /16.384k) * prescaler * (256 - count vaule)
1 system clock timing = ( 2 / system clock) * prescaler* (256 - count vaule)
C1_PSC2 C1_PSC1 C1_PSC0
COUNTER1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Bit 4 ~ Bit 6 (C2_PSC0 ~ C2_PSC2) : COUNTER2 prescaler ratio
C2_PSC2 C2_PSC1 C2_PSC0
COUNTER2 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
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0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
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EPVP6300
VFD Controller
Bit 7 (CNT2S) : COUNTER2 clock source 0 16.384kHz
timing = ( 1 /16.384k) * prescaler * (256 - count vaule)
1 system clock timing = ( 2 / system clock) * prescaler* (256 - count vaule)
7.3.5
Bit 7 IOC97 R/W-1
IOC9 (PORT9 I/O Control)
Bit 6 IOC96 R/W-1 Bit 5 IOC95 R/W-1 Bit 4 IOC94 R/W-1 Bit 3 IOC93 R/W-1 Bit 2 IOC92 R/W-1 Bit 1 IOC91 R/W-1 Bit 0 IOC90 R/W-1
a) PAGE 0 (PORT9 I/O Control Register)
Bit 0 ~ Bit 7 (IOC90 ~ IOC97) : PORT9 (0~7) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin into high impedance
b) PAGE 1 ( Clock Source and Prescaler for COUNTER3 and COUNTER4)
Bit 7 CNT4S R/W-0 Bit 6 R/W-0 Bit 5 R/W-0 Bit 4 R/W-0 Bit 3 CNT3S R/W-0 Bit 2 R/W-0 Bit 1 R/W-0 Bit 0 R/W-0 C4_PSC2 C4_PSC1 C4_PSC0 C3_PSC2 C3_PSC1 C3_PSC0
Bit 0 ~ Bit 2 (C3_PSC0 ~ C3_PSC2) : COUNTER3 prescaler ratio
C3_PSC2 C3_PSC1 C3_PSC0
COUNTER3 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Bit 3 (CNT3S) : COUNTER3 clock source 0 16.384kHz
timing = ( 1 /16.384k) * prescaler * (256 - count vaule)
1 system clock timing = ( 2 / system clock) * prescaler* (256 - count vaule) Bit 4 ~ Bit 6 (C4_PSC0 ~ C4_PSC2) : COUNTER4 prescaler ratio
C4_PSC2 C4_PSC1 C4_PSC0
COUNTER4 1:2 1:4 1:8 1:16 1:32
This specification is subject to change without further notice.
0 0 0 0 1
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0 0 1 1 0
0 1 0 1 0
EPVP6300
VFD Controller
1 1 1
0 1 1
1 0 1
1:64 1:128 1:256
Bit 7 (CNT4S) : COUNTER4 clock source 0 16.384kHz
timing = ( 1 /16.384k) * prescaler * (256 - count vaule)
1 system clock timing = ( 2 / system clock) * prescaler* (256 - count vaule)
7.3.6 IOCA
a) PAGE 1 (Clock Source and Prescaler for COUNTER5 )
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CNT5S R/W-0 Bit 2 R/W-0 Bit 1 R/W-0 Bit 0 R/W-0 C5_PSC2 C5_PSC1 C5_PSC0
Bit 0 ~ Bit 2 (C5_PSC0 ~ C5_PSC2) : COUNTER5 prescaler ratio
C5_PSC2 C5_PSC1 C5_PSC0
COUNTER4 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Bit 3 (CNT5S) : COUNTER5 clock source 0 16.384kHz
timing = ( 1 /16.384k) * prescaler * (256 - count vaule)
1 system clock timing = ( 2 / system clock) * prescaler* (256 - count vaule)
7.3.7 IOCB (PORTB I/O Control, PORTB Switch)
a) PAGE 0 (PORTB I/O Control Register)
Bit 7 R-1 Bit 6 IOCB6 R/W-1 Bit 5 IOCB5 R/W-1 Bit 4 IOCB4 R/W-1 Bit 3 IOCB3 R/W-1 Bit 2 IOCB2 R/W-1 Bit 1 IOCB1 R/W-1 Bit 0 IOCB0 R/W-1
Bit 0 ~ Bit 6 (IOCB0 ~ IOCB 6) : PORTB (0~6) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin into high impedance
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b) PAGE 1 (PORTB Switches)
Bit 7 Bit 6 PB6S R/W-0 Bit 5 PB5S R/W-0 Bit 4 PB4S R/W-0 Bit 3 PB3S R/W-0 Bit 2 PB2S R/W-0 Bit 1 PB1S R/W-0 Bit 0 PB0S R/W-0
Bit 0 (PB0S) : Select between AD Voltage Reference pin or I/O PORTB0 pin 0 1 0 1 PB0 (I/O PORTB0) pin is selected and ADC reference voltage sourced from internal VDD VREF (ADC external reference voltage input) pin is selected PB1 (I/O PORTB1) pin is selected AD1 (ADC Channel 1 input) pin is selected
Bit 1 (PB1S) : Select between normal I/O PORTB1 pin or ADC Channel 1 input AD1 pin
Bit 2 (PB2S) : Select between normal I/O PORTB2 pin or ADC Channel 2 input AD2 pin 0 PB2 (I/O PORTB2) pin is selected 1 AD2 (ADC Channel 2 input) pin is selected Bit 3 (PB3S) : Select between normal I/O PORTB3 pin or ADC Channel 3 input AD3 pin 0 PB3 (I/O PORTB3) pin is selected 1 AD3 (ADC Channel 3 input) pin is selected Bit 4 (PB4S) : Select between normal I/O PORTB4 pin or ADC Channel 4 input AD4 pin 0 PB4 (I/O PORTB4) pin is selected 1 AD4 (ADC Channel 4 input) pin is selected Bit 5 (PB5S) Select between normal I/O PORTB5 pin or ADC Channel 5 input AD5 pin 0 PB5 (I/O PORTB5) pin is selected 1 AD5 (ADC Channel 5 input) pin is selected Bit 6 (PB6S) : Select between normal I/O PORTB5 pin or ADC Channel 6 input AD6 pin 0 PB6 (I/O PORTB6) pin is selected 1 AD6 (ADC Channel 6 input) pin is selected
7.3.8 IOCC (PORTC I/O Control)
a) PAGE 0 (PORTC I/O Control Register)
Bit 7 IOCC7 R/W-1 Bit 6 IOCC6 R/W-1 Bit 5 IOCC5 R/W-1 Bit 4 IOCC4 R/W-1 Bit 3 IOCC3 R/W-1 Bit 2 IOCC2 R/W-1 Bit 1 IOCC1 R/W-1 Bit 0 IOCC0 R/W-1
Bit 0 ~ Bit 7 (IOCC0 ~ IOCC7) : PORTC(0~7) I/O direction control register 0 set the relative I/O pin as output 1 set the relative I/O pin into high impedance
b) PAGE 1 (PORTC Switches)
Bit 7 PC7S R/W-1 Bit 6 PC6S R/W-1 Bit 5 PC5S R/W-1 Bit 4 PC4S R/W-1 Bit 3 Bit 2 Bit 1 Bit 0 -
Bit 4 (PC4S) : Select STB or I/O PORTC4 pin
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VFD Controller
0 1
PC4 (I/O PORTC4) pin is selected STB pin is selected
Bit 5 (PC5S) : Select CLK or I/O PORTC5 pin 0 PC5 (I/O PORTC5) pin is selected 1 CLK pin is selected Bit 6 (PC6S) : Select DOUT or I/O PORTC6 pin 0 PC6 (I/O PORTC6) pin is selected 1 DOUT pin is selected (N-channel,Open-Drain) Bit 7 (PC7S) : Select DIN or I/O PORTC7 pin 0 PC7 (I/O PORTC7) pin is selected 1 DIN pin is selected
7.3.9 IOCD (Interrupt Mask, Prescaler of CN3 ~ CN5)
a) PAGE 0 (Interrupt Mask)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CNT5 R/W-0 Bit 1 CNT4 R/W-0 Bit 0 CNT3 R/W-0
Bit 0 ~ 3 : Interrupt enable bit 0 disable interrupt 1 enable interrupt
7.3.10 IOCE (Interrupt Mask)
a) PAGE 0 (Interrupt Mask)
Bit 7 Bit 6 RBF R/W-0 Bit 5 ADI R/W-0 Bit 4 STB R/W-0 Bit 3 Bit 2 Bit 1 Bit 0 -
Bit 4 (STB) : STB goes LOW interrupt mask. 0/1 disable/enable interrupt Bit 5 (ADI) : ADC interrupt flag after a sampling 0/1 disable/enable interrupt
Bit 6 (RBF) : SPI's RBF interrupt mask 0/1 disable/enable interrupt
7.3.11 IOCF (Interrupt Mask )
a) PAGE 0 (Interrupt Mask Register)
Bit 7 INT4 R/W-0 Bit 6 INT3 R/W-0 Bit 5 INT2 R/W-0 Bit 4 INT1 R/W-0 Bit 3 IR R/W-0 Bit 2 CNT2 R/W-0 Bit 1 CNT1 R/W-0 Bit 0 TCIF R/W-0
Bit 0 ~ 7: Interrupt enable bit 0 disable interrupt 1 enable interrupt The status after interrupt and the interrupt source lists are as shown in the table below.
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Interrupt Signal + SLEP TCC time out IOCF bit0=1 And "ENI"
IDLE Mode RA(7,6)=(1,0) 1) Wake-up 2) Interrupt (jump to Address 8 on Page0) 3) After RETI instruction, jump to SLEP Next instruction
GREEN Mode RA(7,6)=(x,0) no SLEP Interrupt (jump to Address 8 on Page0)
NORMAL Mode RA(7,6)=(x,1) no SLEP Interrupt (jump to Address 8 on Page0)
1) Wake-up COUNTER1 time out 2) Interrupt (jump to Address 8 on Page0) IOCF bit1=1 3) After RETI instruction, jump to And "ENI" SLEP Next instruction 1) Wake-up COUNTER2 time out 2) Interrupt (jump to Address 8 on IOCF bit2=2 Page0) And "ENI" 3) After RETI instruction, jump to SLEP Next instruction
Interrupt (jump to Address 8 on Page0)
Interrupt (jump to Address 8 on Page0)
Interrupt (jump to Address 8 on Page0)
Interrupt (jump to Address 8 on Page0)
1) Wake-up COUNTER3 time out 2) Interrupt (jump to Address 8 on IOCD bit0=1 Page0) And "ENI" 3) After RETI instruction, jump to SLEP Next instruction
Interrupt (jump to Address 8 on Page0)
Interrupt (jump to Address 8 on Page0)
1) Wake-up COUNTER4 time out 2) Interrupt (jump to Address 8 on IOCD bit1=1 Page0) And "ENI" 3) After RETI instruction, jump to SLEP Next instruction
Interrupt (jump to Address 8 on Page0)
Interrupt (jump to Address 8 on Page0)
1) Wake-up COUNTER5 time out 2) Interrupt (jump to Address 8 on IOCD bit2=1 Page0) And "ENI" INT1~4 3) After RETI instruction, jump to SLEP Next instruction 1) Wake-up
Interrupt (jump to Address 8 on Page0)
Interrupt (jump to Address 8 on Page0)
IOCF bit4=1 or IOCF 2)Interrupt (jump to Address 8 on bit5=1 IOCF bit6 = 1 Page0) or IOCF bit7= 1 3) after RETI instruction, jump to And "ENI SLEP Next instruction 1) Wake-up IR IOCF bit3= 1 And "ENI ADI IOCE bit5 = 1 And "ENI RBF IOCE bit6 = 1 30 of 63
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Interrupt (jump to Address 8 on Page0)
Interrupt (jump to Address 8 on Page0)
2) Interrupt (jump to Address 8 on Page0) 3) After RETI instruction, jump to SLEP Next instruction No function
Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8
Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8 on Page0) Interrupt (jump to Address 8
No function
This specification is subject to change without further notice.
EPVP6300
VFD Controller
And "ENI STB IOCE bit4 = 1 And "ENI No function
on Page0) Interrupt (jump to Address 8 on Page0)
on Page0) Interrupt (jump to Address 8 on Page0)
NOTES: 1. PORT90 interrupt function is controlled by IOCF Bit 3. It is a falling edge or rising edge trigger (controlled by CONT register Bit7). 2. PORT9 (1~4) interrupt functions are controlled by IOCF Bits 4, 5, 6, & 7). They are falling edge triggers. 3. STB interrupt source function is controlled by IOCE PAGE0 Bit 4. It is falling edge trigger after the STB goes low.
7.4 Application notes
1B Call-table instruction:G
Because the call-table instruction can only change the Program Counter's bit7 ~ bit0 at each time, only 256 addresses can be searched once. But each program page contains 1024 addresses, if call each 256 addresses as a zone, Then each page constitutes by four zones. When a table overlaps two zones, a bug would occur during address searching. So the member of program must examine the .LST file at any time, the .LST file will jot down the information that Assembler generated, for example source code, the coding of instruction , instruction address, error message etc.
2B Operation requirement for the CPUG
The system frequency must adds a latency time ( 14.33 MHz about 250 ms F 17.91 MHz about 450 ms.). After RA register was setting, it will offer the stable system frequency for the operation.
This specification is subject to change without further notice.
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7.5 I/O Port
The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers under program control. The I/O data registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig.22.
PCRD
Q
P R C L
D CLK PCWR
Q
PORT
Q
P R C L
D CLK PDWR
IOD
Q
PDRD 0 1 M U X
Fig. 8 The Circuit of I/O Port and I/O Control Register
7.6 RESET
A RESET can be caused by any of the following: 1. Power on reset 2. WDT timeout (if enabled and in GREEN or NORMAL mode) 3. /RESET pin pull low Once a RESET occurs, the following functions are performed. The oscillator is running, or will be started. The Program Counter (R2) is set to all "0". When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared. The Watchdog timer and prescaler counter are cleared. The Watchdog timer is disabled. The CONT register is set to all "1"
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VFD Controller
The other registers' (Bit 7 ~ Bit 0) default values are as follows.
Address 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF R Register PAGE 0 00xxxxxx 0000xxxx 00000000 00000000 00000000 00000000 00011xx0 00000000 1011xxxx xxxxx000 X0000000 00000000 00000000 00000000 xxxxxxxx xxxxxxxx 00000000 00000000 xxxx0000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx x1111111 1111xxxx xxxxx000 x000xxxx 00000000 11111111 00000000 00000000 00000000 x0000000 1111xxxx R Register PAGE 1 R Register PAGE 2 R Register IOC Register IOC Register PAGE 3 PAGE 0 PAGE 1
7.7 Wake Up
The controller features two types of sleep mode for power saving:
7.7.1 SLEEP Mode, RA(6 ;7) = 0 + "SLEP" Instruction
Under this mode, the controller turns off all the CPU and crystal. However, other circuits with power control like key tone control or PLL control (with register enabled), has to be turned off through software.
7.7.2 IDLE mode, RA(6 ;7) = 1 + "SLEP" Instruction.
With this mode, the controller only turns the CPU off. The crystal remains running.
7.7.3 Wake-up from SLEEP Mode
1. WDT time out 2. External interrupt 3. /RESET pull low Any of these cases will reset the controller and run the program from address zero. The status is just like the power-on-reset condition. Be sure to enable circuit after cases 1 or 2 occurs.
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7.7.4 Wake-up from IDLE Mode
1. WDT time out 2. External interrupt 3. Internal interrupt like counters All these cases requires you to enable the circuit before entering IDLE mode. All the registers values are preserved when "SLEP" instruction is executed and restored after wake-up. During execution of case 2 or 3, controller will wake up and jump to address 0x08 for interruption sub-routine. After performing the sub-routine ("RETI" instruction), the program will jump to the next instruction following the "SLEP" instruction.
7.8 Interrupts
RD, RE, and RF are the interrupt status registers which record the interrupt request in flag bit. IOCD, IOCE, & IOCF are their interrupt mask registers respectively. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled) is generated, it will cause the next instruction to be fetched from address 008H. Once in the interrupt service routine, the source of the interrupt can be determined by polling the flag bits in their respective (RD, RE, and RF) registers. The interrupt flag bit must be cleared in the software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts.
7.9 Instruction Set
The Instruction set has the following features: 1. Every bit of any register can be set, cleared, or tested directly. 2. The I/O register can be treated as a general register. That is, the same instruction can operates on I/O register. The symbol "R" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit located in the Register "R," and affected by the operation. "k'' represents an 8 or 10-bit constant or literal value.
Instruction Binary 0 0000 0000 0000 0 0000 0000 0001 0 0000 0000 0010 0 0000 0000 0011 0 0000 0000 0100 0 0000 0000 rrrr 0 0000 0001 0000 34 of 63
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HEX 0000 0001 0002 0003 0004 000r 0010
Mnemonic NOP DAA CONTW SLEP WDTC IOW R ENI
Operation No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt
Status Affected None C None T,P T,P None None
Instruction Cycle 1 1 1 1 1 1 1
This specification is subject to change without further notice.
EPVP6300
VFD Controller
0 0000 0001 0001 0 0000 0001 0010 0 0000 0001 0011 0 0000 0001 0100 0 0000 0001 rrrr 0 0000 0010 0000 0 0000 01rr rrrr 0 0000 1000 0000 0 0000 11rr rrrr 0 0001 00rr rrrr 0 0001 01rr rrrr 0 0001 10rr rrrr 0 0001 11rr rrrr 0 0010 00rr rrrr 0 0010 01rr rrrr 0 0010 10rr rrrr 0 0010 11rr rrrr 0 0011 00rr rrrr 0 0011 01rr rrrr 0 0011 10rr rrrr 0 0011 11rr rrrr 0 0100 00rr rrrr 0 0100 01rr rrrr 0 0100 10rr rrrr 0 0100 11rr rrrr 0 0101 00rr rrrr 0 0101 01rr rrrr 0 0101 10rr rrrr 0 0101 11rr rrrr 0 0110 00rr rrrr 0 0110 01rr rrrr 0 0110 10rr rrrr 0 0110 11rr rrrr 0 0111 00rr rrrr 0 0111 01rr rrrr
0011 0012 0013 0014 001r 0020 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr
DISI RET RETI CONTR IOR R TBL MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R
Disable Interrupt [Top of Stack] PC [Top of Stack] PC Enable Interrupt CONT A IOCR A AR 0A 0R R-A A R-A R R-1 A R-1 R ARA ARR A&RA A&RR ARA ARR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1) R(0) C, C A(7) R(n) R(n-1) R(0) C, C R(7) R(n) A(n+1) R(7) C, C A(0) R(n) R(n+1) R(7) C, C R(0) R(0-3) A(4-7) R(4-7) A(0-3) R(0-3) R(4-7)
None None None None None
1 2 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 if skip 2 if skip 1 1 1 1 1 1
R2+A R2 bits 9,10 do not clear Z,C,DC None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None C C C C None None
This specification is subject to change without further notice.
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0 0111 10rr rrrr 0 0111 11rr rrrr 0 100b bbrr rrrr 0 101b bbrr rrrr 0 110b bbrr rrrr 0 111b bbrr rrrr 1 00kk kkkk kkkk 1 01kk kkkk kkkk 1 1000 kkkk kkkk 1 1001 kkkk kkkk 1 1010 kkkk kkkk 1 1011 kkkk kkkk 1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1110 0000 0001 1 1110 100k kkkk 1 1111 kkkk kkkk
07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1E8k 1Fkk
JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT PAGE k ADD A,k
R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP] (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1 [SP] 001H PC K->R5(4:0) k+A A
None None None None None None None None None Z Z Z None Z,C,DC None None Z,C,DC
2 if skip 2 if skip 1 1 2 if skip 2 if skip 2 2 1 1 1 1 2 1 1 1 1
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VFD Controller
7.10Bonding Coordinates Subsidiary
Chip size : SubstrateG P substrate Chip size G 2710 *2580 uM
7.10.1 Pad Configuration
Fig. 9 EPVP6300 Pad Configuration
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7.10.2 Pad Name and Coordinates Table
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VFD Controller
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8
Segment Data Buffers
The EPVP6300 chip provides a total of 256 bytes data RAM. On the other hand, display Segment Data Buffers can be stored either in the data RAM of 256 bytes sizes (00h~40h) or in the common registers of Bank 2 and Bank 3 (20h~3Fh).
a) Data RAM Address
00h~38h 39h~3Eh 3Fh 40h 57X8 Segment Data Buffers 6X8 Key Scanning Data Buffers SW data register LED data register
b) Common Registers Address
20 : 3F Bank0~Bank3 Common registers (32x8 for each bank)
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VFD Controller
These buffers store display RAM. The display RAM stores the data transmitted from an external device to the EPVP6300 through the serial interface and is assigned addresses as follows, in units of 8 bits:
b0 b3 b4 b7
X X HL
Lower 4 bits
X X HU
Higher 4 bits
Only the lower 4 bits of the addresses assigned to SEG17 through SEG20 are valid and the higher 4 bits are ignored.
c) Display Memory Addresses:
Seg1 Seg4 Seg8 00 HU 03 HU 06 HU 09 HU 0C HU 0F HU 12 HU 15 HU 18 HU 1B HU 1E HU 21 HU 24 HU 27 HU 2A HU 2D HU 30 HU 33 HU 36 HU Seg12 01 HL 04 HL 07 HL 0A HL 0D HL 10 HL 13 HL 16 HL 19 HL 1C HL 1F HL 22 HL 25 HL 28 HL 2B HL 2E HL 31 HL 34 HL 37 HL Seg16 01 HU 04 HU 07 HU 0A HU 0D HU 10 HU 13 HU 16 HU 19 HU 1C HU 1F HU 22 HU 25 HU 28 HU 2B HU 2E HU 31 HU 34 HU 37 HU Seg20 02 HL 05 HL 08 HL 0B HL 0E HL 11 HL 14 HL 17 HL 1A HL 1D HL 20 HL 23 HL 26 HL 29 HL 2C HL 2F HL 32 HL 35 HL 38 HL DIG1 DIG2 DIG3 DIG4 DIG5 DIG6 DIG7 DIG8 DIG9 DIG10 DIG11 DIG12 DIG13 DIG14 DIG15 DIG16 DIG17 DIG18 DIG19 00 HL 03 HL 06 HL 09 HL 0C HL 0F HL 12 HL 15 HL 18 HL 1B HL 1E HL 21 HL 24 HL 27 HL 2A HL 2D HL 30 HL 33 HL 36 HL
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b)
Key Scanning Data Buffers:
KEY1 KEY2 KEY3 KEY4
SEG1/KS1
SEG2/KS2
SEG3/KS3
SEG4/KS4
SEG5/KS5
SEG6/KS6
SEG7/KS7
SEG8/KS8
SEG9/KS9
SEG10/KS10
SEG11/KS11
Fig. 10 12 x 4 Configuration Key Matrix
The key matrix is of 12 x 4 configuration is as shown in the above figure. The data of each key is stored as illustrated below, and is read by a read command, starting from the least significant bit.
KEY1....KEY4 SEG1/KS1 SEG3/KS3 SEG5/KS5 SEG7/KS7 SEG9/KS9 SEG11/KS11 b0 -- -- b3 KEY1....KEY4 SEG2/KS2 SEG4/KS4 SEG6/KS6 SEG8/KS8 SEG10/KS10 SEG12/KS12 b4 -- -- b7
Reading sequence
When the most significant bit of data (SEG12, b7) has been read, the least significant bit of the next data (SEG1, b0) is read.
8.1 Commands
A command sets the display mode and status of the VFD driver. The first 1 byte (b0 to b7) inputted to the EPVP6300 through the DIN pin after the STB pin has fallen, is regarded as a command. Interrupt event will occur when STB pin is falling. If STB mode is high while a command/data are being transmitted, serial communication is initialized, and the command/data being transmitted is invalidated (however, the command/data already transmitted remain valid).
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SEG12/KS12
EPVP6300
VFD Controller
8.1.1 Display Mode Setting Command [00]
This command initializes the EPVP6300 and selects Display mode number of segments and grids (1/8 to 1/19-duty, 9 segments to 20 segments) as illustrated below. When Display Mode command is executed, display is forcibly turned off, and key scanning is also stopped. To resume display, a display ON command must be executed. If the same Display mode is selected, nothing is performed. When power is turned "ON," default Display mode is "19-digit, 9-segment."
MSB
b7 0
b6 0
b5 0
b4 0
b3 1
b2 1
b1 1
b0 1
LSB Initial value
Display mode Not Relevant
0000 : 8 digits, 20 segments. 0001 : 9 digits, 19 segments. 0010 : 10 digits, 18 segments. 0011 : 11 digits, 17 segments. 1000 : 12 digits, 16 segments. 1001 : 13 digits, 15 segments. 1010 : 14 digits, 14 segments. 1011 : 15 digits, 13 segments. 1100 : 16 digits, 12 segments. 1101 : 17 digits, 11 segments.
Default setting
1110 : 18 digits, 10 segments. 1111 : 19 digits, 9 segments.
Fig. 11 Display Mode Setting Command Selection
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8.1.2 Data Setting Command [01]
This command sets data write and data read modes. The default settings at power "ON" are: Address Increment Mode: "Address increment mode." Test Mode: "Normal operation mode."
MSB b7 0 b6 1 b5 0 b4 0 b3 0 b2 0 b1 0 b0 0 LSB Initial value
Not Relevant
00 : Write data to display memory. 01 : Write data to LED port. 10 : Read key port switch data 11 : Read switch status.
Sets address increment mode (display memory) 0 : Increments address after data has been written. 1 : Fixes address.
Fig. 12 Data Setting Command Selection
8.1.3 Display Control Command [10]
When power is turned "ON," the following default conditions prevails: 4/64-pulse width is set and the display is turned off Key & switch scanning is stopped
MSB
b7 1
b6 0
b5 0
b4 0
b3 0
b2 0
b1 0
b0 0
LSB Initial value
Turns on/off display. 0 : Display off (key & switch scan continues) 1 : Display on.
Sets dimming 000 : Sets pulse width to 1/16 001 : Sets pulse width to 2/16 010 : Sets pulse width to 4/16 011 : Sets pulse width to 10/16 100 : Sets pulse width to 11/16 101 : Sets pulse width to 12/16 110 : Sets pulse width to 13/16 111 : Sets pulse width to 14/16
Fig. 13 Display Control Command Selection 44 of 63
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VFD Controller
8.1.4 Address Setting Command [11]
This command sets an address of the display memory. When power is turned "ON", the default address is set to 00H.
MSB b7
b6 1
b5
b4
b3 0
b2 0
b1 0
b0 0
LSB Initial value
1
0
0
Address ( 00H - 38H )
Fig. 14 Address Setting Command Selection
If address 39H or higher is set, the data is ignored until a correct address is set.
This specification is subject to change without further notice.
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EPVP6300
VFD Controller
9
RC/Crystal OSC
9.1 General Description
This oscillator is designed for the EPVP6300 chip as clock source.
9.2 Features
RC oscillator: 32.768K Hz Operating voltage: 2.2~5.5V. Operating temperature: -20 C ~ 70 C
o o
9.3 Block Diagram
VDD XOUT CRYXRC 27 pf 470 Kohm OSCI 32768 KHz 27 pf
OSCI VSS
XOUT
Fig. 15 RC/Crystal OSC Block Diagram
9.4 Pin Description
Name I/O Type Description Remarks
XIN XOUT VDD VSS
I O -
Crystal or RC oscillator connection pin Crystal oscillator output pin Power supply (+) pin Power supply (-) pin
9.5 Electrical
(Condition : VDD = 4.5 to 5.5V, Ta = -20C to 70C )
Parameters Sym. Min. Typ. Max. Unit Conditions
Starting oscillation voltage Stable time Current consumption Duty cycle Frequency/Voltage deviation Frequency/Temperature deviation Frequency vs. Process deviation
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Vs Ts Idd
f/V f
45 -
2.0 5 2 50 1 1
6
3.2 10 3 55 1.5 2
10
V clk mA % % % % Vdd = 5.0V Vdd = 5.0V
This specification is subject to change without further notice.
EPVP6300
VFD Controller
10 Absolute Operation Maximum Ratings
Absolute maximum ratings (Ta = 25C, Vss = 0 V)
Parameter Symbol Ratings Unit
Logic supply voltage Driver supply voltage Logic input voltage VFD driver output voltage LED driver output current VFD driver output current Operating ambient temperature Storage temperature
VDD VEE VI VO IO1 IO2 Topt Tstg
-0.5 to + 6 VDD +0.5 to VDD - 45 -0.5 to VDD +0.5 VEE -0.5 to VDD +0.5 +25 -40 (Grid) -15 (Segment) -40 to +85 -65 to +150
V V V V mA mA
C C
11 DC Electrical Characteristic (Ta = -20 to +70C, VDD = 4.5 to 5.5V, Vss = 0V, VEE = VDD - 45V)
Parameter Symbol Min. Typ. Max. Unit Test conditions
GPIOB
Digital Input Voltage High Digital Input Voltage Low Schmitt Trigger Negative Going Threshold Voltage Schmitt Trigger Positive Going Threshold Voltage Input Leakage Current Pull Up Resister Digital Output Voltage High Digital Output Voltage Low Digital Output High Current Digital Output Low Current Digital Output High Current Digital Output Low Current HV Output Current
VIH IOL VTVT+ IIN RPU VOH VOL IOH1 IOL1 IOH2 IOL2 IOH1
0.8VDD VSS 1.5 2.9 50 0.8VDD VSS -2 2 -15 15 -6
1.8 3.2 75 -4 4 -18 18 -4
VDD 0.2VDD 2.1 3.5
O 1
V V
V uA K[ V V mA mA mA mA mA
GPIOC, GPO9, CLK, STB, DIN and /RESET,GPIOB GPIOB, VIN = VDD or VSS GPIOC, GPO9, CLK, STB, DOUT, DIN , CRYXRC and /RESET @ VDD=5V DOUT, GPIOB, GPIOC VOH=2.4V / DOUT, GPIOB, GPIOC VOL=0.4V / DOUT, GPIOB, GPIOC VOH=2.4V / GPIO9 VOL=0.4V / GPIO9 Vo = VDD -2V,(VDD=5V) SEG1/KS1 to SEG4/KS4, P24/SG5/KS5 to P20/SG9/KS9. Vo = VDD -2V,(VDD=5V)
100 VDD 0.2VDD -5 5 -25 25 -3
HV Output Current
IOH2
-15
-13
-11
mA
GR1/P1 to GR8/P8, GR9/P9/SG20 to GR16/P16/SG13,
This specification is subject to change without further notice.
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EPVP6300
VFD Controller
GR17/P17/SG12/KS12 to GR19/P19/SG10/KS10 HV leakage current HV Output pull-down resistor Power down current (SLEEP mode) Low clock current (GREEN mode) IHVLEAK RL ISB1 5 40 8 80 10 120 1.5 uA K
A
Vo = VDD -45V, driver off Driver output (VEE= -25V) All input and I/O pin at VDD, output pin floating, WDT disabled VDD =3V CLK=32.768KHz, all analog circuits disabled, all input and I/O pin at VDD, output pin floating VDD =5V CLK=32.768KHz, all analog circuits disabled, all input and I/O pin at VDD, output pin floating VDD =3V CLK=32.768KHz, all analog circuits disabled, all input and I/O pin at VDD, output pin floating VDD =5V CLK=32.768KHz, all analog circuits disabled, all input and I/O pin at VDD, output pin floating /RESET=High, CLK=3.582MHz, all analog circuits disabled, output pin floating
30 ISB2 65
60
A
Crystal oscillation operating mode
Low clock current (IDLE mode)
Crystal oscillation operating mode
90
A
30 ISB3 45
45
A
60
A
Operating supply current (Normal mode)
Crystal oscillation operating mode
ICC
1.3
2
mA
12 AC Electrical Characteristic
12.1 CPU Instruction Timing (Ta = -20C ~ 70C, VDD=5V, VSS=0V)
Parameter Symbol Condition Min Typ Max Unit
Input CLK duty cycle Instruction cycle time Device delay hold time TCC input period Watchdog timer period
Dclk Tins Tdrh Ttcc Twdt Note 1 Ta = 25C 32.768kHz 3.582MHz
45
50 60 550 16
55
% us ns ms ns
(Tins+20)/N 16
ms
NOTE: N= selected prescaler ratio
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This specification is subject to change without further notice.
EPVP6300
VFD Controller
12.2 AC Timing Characteristic (VDD=5V, Ta=+25C)
Description Symbol Min Typ Max Unit
Oscillator timing characteristic OSC start up 32.768kHz 3.579MHz PLL Tosc 400 5 1500 10 ms us
SPI timing characteristic (CPU clock 3.58MHz and Fsco = 3.582Mhz /2) /SS set-up time /SS hold time SCLK high time SCLK low time SCLK rising time SCLK falling time SDI set-up time to the reading edge of SCLK SDI hold time to the reading edge of SCLK SDO disable time Tcss Tcsh Thi Tlo Tr Tf Tisu Tihd Tdis 25 25 560 560 250 250 250 15 15 30 30 ns ns ns ns ns ns ns ns
12.3 EPVP6300 Operating Voltage VS main clock
(X Axis Min VDD ; Y Axis Main CLK)
MHz 17.91 14.33 10.74 7.16 3.58 1.79
2.2
3
3.3
4
5
5.5
V
Fig. 16 Operation Voltage XY Axis
This specification is subject to change without further notice.
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EPVP6300
VFD Controller
12.4 AC Timing Diagrams
Fig. 17a A/C Test Input/Output Waveform
Fig. 17b RESET Timing Diagram
ins
Fig. 17c TCC Input Timing Diagram
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This specification is subject to change without further notice.
EPVP6300
VFD Controller
13 Key & Switch Scanning and Display Timing
The key & switch scanning and display timing diagram is given below. One cycle of key & switch scanning consists of 2 frames. The data of the 12 x 4 matrix is stored in the RAM.
31.25 us 470 us 500 us
GRID 1 output
1/16 4/16 6/16 8/16 10/16 12/16 14/16
16/16
GRID 2 output SEG 1 output SEG 2 output SEG 3 output
DISP U 500us Key & Switch scan data
GRID 1 output GRID 2 output GRID 3 output GRID n output
SEG1 output SEG2 output SEG3 output SEGn output
GRID 1
GRID 2
GRID 3
GRIDn
DIG1
1/16
4/16
10/16
2/16
14/16 2/16
1 frame = TISP *(n+1) D
Fig. 18 Key & Switch Scanning and Display Timing Diagram
This specification is subject to change without further notice.
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EPVP6300
VFD Controller
14 Serial/Parallel Communication Format
14.1 Reception (Command/Data Write)
If data is contiguous STB
DIN
b0
b1
b2
b6
b7
CLK
1
2
3
7
8
Fig. 19 Data Reception Timing Diagram
14.2 Transmission (Data Read)
ST DI DOU CL 1 2 3 4 5 6 7 8 * tWAIT Data reading
Fig. 20 Data Transmission Timing Diagram When data is read, a wait time "tWAIT" is necessary between the rising of the eighth clock that has set the command and the falling of the first clock that has read the data.
NOTE: The wait time is adjustable according to different applications.
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 1 2 3 4 5 6
Data reading
15 Switching Characteristic Waveform
f OSC OSC 50 %
Fig. 21a Switching Characteristic Waveform
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This specification is subject to change without further notice.
EPVP6300
VFD Controller
PWSTB STB PWCLK CLK t SETUP Data in t PZL Data out tTHZ 90% Sn/Gn 10% t TZH t PLZ t HOLD PWCLK t CLKSTB
Fig. 21b Switching Characteristic Timing Diagram
15.1 Switching Characteristics (Ta = - 20 to + 70C, VDD = 4.5 to 5.5V, VEE = VDD - 45V)
Parameter Symbol Min. Typ. Max. Unit Test Conditions
Oscillation frequency Propagation delay time
tOSC tPLZ tPZL tTZH1
-
32.768 -
300 100 2
KHz ns ns us CLKDOUT CL = 15pF, RL = 10K
-
SEG1/KS1 to SEG4/KS4,
SG5/KS5 to SG9/KS9. CL = 100Pf GR1 to GR8 VEE=-25V GR9/SG20 to
Rise time tTZH2 0.5
s
GR9/ SG13,
GR17/SG12/KS12 to GR19/SG10/KS10
Fall time Data input clock freq. Input capacitance Clock pulse width Strobe pulse width Data setup time Data hold time Clock-Strobe time Wait time
tTHZ fmax CI PWCLK PWSTB tSETUP tHOLD tCLKSTB tWAIT
100 -
110 1
120 1.25 15
s
CL = 100pF, VEE=-25V,SEGn, GRIDn Duty = 50 %, CLK
MHz pF ns
s
400 0.8 100 100 0.8 -
500 1 1 -
-
ns ns
s s
CLKSTB CLKCLK*
This specification is subject to change without further notice.
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EPVP6300
VFD Controller
16 Serial I/F Sets Display Data Sequence
16.1 Updating Display Memory by Incrementing Address
STB CLK Data input Command1 Command2 Command3 Data 1 Data n Command4
Fig. 22 incrementing Address Timing Diagram Where:
Command 1 Command 2 Command 3 Data 1 to n Command 4 : Display mode : Sets data : Sets address : Transfers display data (57 bytes max.) : Controls display
16.2 Updating Specific Address
STB CLK Data input Command2 Command3 Data Command3 Data n
Fig. 23 Specific Address Timing Diagram Where:
Command 2 Command 3 Data : Sets data : Sets address : Display data
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This specification is subject to change without further notice.
EPVP6300
VFD Controller
17 Application
17.1 VFD Controller for DVD Player
Front-end Back-end
SDRAM
RF
Servo Controller
Bitstream
MMU
VPU 4 STB,DIN,DOUT,CLK ePV6300 VFD Controller X86/51 /RISC
APU
FLASH
IR
Fig. 23 Block Diagram for DVD Player Application
17.2 VFD Controller for Cascade Applaication
Din,Dout,CLK,STB 4
SPI
4
SPI
I/O
4
SPI
ePV6300
ePV300
ePV6300
DVD/DVR 27s~8s 1G~19G Grid 28 Segment 28
Fig. 24 Block Diagram for Cascade Application
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EPVP6300
VFD Controller
17.3 APPLICATION CIRCUIT
R1 1k DOUT RN1 5 6 7 8 C4 0.01uf VSS OSCI R1 470k /RESET 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 C3 0.1uf /RESET VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 4 3 2 1 VSS 8P4R 100 1 2 3 4 5 OSCI OSCO VDD JP1 DIN DOUT STB CLK VSS SPI connect VDD
CRYSTAL1 32.768KHz C6 27pf C5 27pf
VSS OSCO VSS AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OSCO CRYXRC VSS AVSS GPIOB0 GPIOB1 GPIOB2 GPIOB3 GPIOB4 GPIOB5 GPIOB6 AVDD VDD1 VDD2 GR1 GR2
OSCI PLLC NC62 NC61 DIN DOUT CLK STB GPIOC3 GPIOC2 GPIOC1 GPIOC0 GPIO97 GPIO96 GPIO95 GPIO94
ePV6300 LQFP
AVDD VDD 0.1uf C1
VSS
L1 VCC L2 VSS INDUCTOR IRON (FB) C7 4.7uF/16V C8 0.1uf AVSS AVDD
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17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GR3 GR4 GR5 GR6 GR7 GR8 GR9/SG20 GR10/SG19 GR11/SG18 GR12/SG17 GR13/SG16 GR14/SG15 GR15/SG14 GR16/SG13 GR17/SG12/KS12 GR18/SG11/KS11
GPIO93 GPIO92 GPIO91 GPIO90 /RESET VEE SG1/KS1 SG2/KS2 SG3/KS3 SG4/KS4 SG5/KS5 SG6/KS6 SG7/KS7 SG8/KS8 SG9/KS9 GR19/SG10/KS10
VEE
C2 0.1uf VSS
This specification is subject to change without further notice.
EPVP6300
VFD Controller
Package Information
(1) Package Type: Plastic LQFP-64
DETAIL " A " D D1
L
L1
64
Symbal A A1 A2 D D1 E E1 e c c1 b b1 L L1
Min 0.05 1.35 8.90 6.90 8.90 6.900 0.09 0.09 0.13 0.13 0.45 0
1 b
e
c
Normal 1.40 9.00 7.00 9.00 7.00 0.4 BSC 0.18 0.16 0.60 1.00 REF. 3.5
Max 1.60 0.15 1.45 9.10 7.10 9.10 7.100 0.20 0.16 0.23 0.19 0.75 7
E E1
A2 A1
DETAIL " B "
c1
b b1
A
c
This specification is subject to change without further notice.
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